Pipeline Hazards

本文主要是介绍Pipeline Hazards，对大家解决编程问题具有一定的参考价值，需要的程序猿们随着小编来一起学习吧！

数据依赖RAW WAW WAR

流水线有这样一种情况：在下一个时钟周期中下一条指令不能执行。这种情况叫做冒险。流水线冒险包括以下三种：

1. 结构冒险（structural hazard）:(resource)
   如果有两个不同的stage需要访问同一个资源，那它俩就不能并行运行了，这时候有的就只能wait。这叫结构冒险
   一个好点的解决方法就是create duplicate resource

2. 数据冒险（data hazard）
   因无法提供指令执行所需数据而导致指令不能在预定的时钟周期内执行。也就是第二条指令需要第一条指令完成后才能运行（比如需要第一步算出来的结果）。这个也叫做data dependence
   有三种data dependence：

Read after Write
Write after Read
Write after Write
只有第一种是true dependence，别的都可以通过一些方法解决（比如duplicate resource之类）。
对于Read after Write，就只能确保read指令必须要在write完成之后才能开始。这时在两条语句执行的中间就需要Stalling。也就是delay instruction until hazard is resolved。

stall的实现是通过对不同部件发送以下三种control signal来实现的：

“Transfer” (normal operation) indicates should transfer next state to current
“Stall” indicates that current state should not be changed
“Bubble” indicates that current state should be set to 0

3. 控制冒险（control hazard）
   Conditional branches cause uncertainty to instruction sequencing. 这样只有conditional branch算出来之后才能fetch next instruction。

4. 超流水线（superpipelining）：更多的stage

5. 超标量（superscalar）：一次fetch多条指令
   超标量（Super Scalar) 将一条指令分成若干个周期处理以达到多条指令重叠处理，从而提高cpu部件利用率的技术叫做标量流水技术。 超级标量是指cpu内一般能有多条流水线，借助硬件资源重复（例如有两套译码器和ALU等）来实现空间的并行操作。

llvm/lib/Target/DTU/MCTargetDesc/DTUMCInstrInfo.cpp

// if MCInsts has certain data dependencies with instruction existed in
// packet, it can not be added into packet
//
// Generally, for below example:
//
// A: DEF R1, USE R3
// B: DEF R3, USE R2
// C: DEF R4, USE R3
// D: DEF R4, USE R5
//
// (Case 0) A & B can be packeted together. This because WAR on R3 is (write after read)
// guarateed by HW when being issued in same cycle. (all the
// engine types include scalar, 1d, 2d)
//
// (Case 1) B & C can not be packeted together. RAW on R3 is surely
// broken.
//
// (Case 2) C & D can not be packeted together. WAW on R4 could be
// broken.
//
// In current assumption,
// S1. Compilation path or auto packetizing (llvm-mc). “Inst” is sequenced
// after instructions existed in packet. It requires to check RAW
// (Case 1) on its uses & defs, and WAW (Case 2) on its defs.
// S2. “bracketed mode”. It implies either “Inst” happens-before existed
// instructions, or existed instructions happens-before “Inst” is
// reasonable. Checking for WAW (Case 2) is a must. RAW should be warned.
// (as there is no order in packet, it could also appears like WAR)
// S3. “VAB” registers may modify the base of VA registers. Packetizer
// would be PESSIMISTIC reporting NO HAZARD, unless it explicit claim
// “SameVAB”.

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