JM-S03061AH-002 verilog 驱动程序

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 JM-S03061AH-002 数码管显示控制模块代码设计

指标
刷新率100hz
Seven_Segment_Code_Out--显示字符字长8bit
Bit_Sel_Out--片选信号6bit

//Seven_Segment_Numeric_LED_Disp for mini fpga
//by chunk998 2021-12-16 fixed
// add dot support

module Seven_Segment_Numeric_LED_Disp
(
CLK, RSTn, idata_valid,oData_fetched,iLed_SixCode, Seven_Segment_Code_Out, Bit_Sel_Out
);
input CLK, RSTn, idata_valid;
input [29:0] iLed_SixCode;
output [7:0] Seven_Segment_Code_Out;
output [5:0] Bit_Sel_Out;
output oData_fetched;

////////////////////////////
parameter bit_5 = 6'b11_1110,
bit_4 = 6'b11_1101,
bit_3 = 6'b11_1011,
bit_2 = 6'b11_0111,
bit_1 = 6'b10_1111,
bit_0 = 6'b01_1111,
bit_dark = 6'b11_1111,
bit_all = 6'b00_0000;

reg [4:0] Single_Seven_Segment_Code;
wire [29:0] Led_SixCode;
wire [29:0] Led_SixCode_TMP;

wire [5:0] BIT_CS_Current;
wire clk_600hz = CLK;

assign oData_fetched = idata_valid == 1'b1 && BIT_CS_Current == bit_1;

chunk_dff #(30) eHEX_SixNum_DFF(.CLK(clk_600hz),.D(Led_SixCode_TMP),.Q(Led_SixCode));

assign Led_SixCode_TMP = RSTn == 1'b0 ? 30'b0 :
(idata_valid ==1'b1 && BIT_CS_Current == bit_0 ? Led_SixCode : Led_SixCode_TMP);

parameter _0 = 8'b0011_1111, _1 = 8'b0000_0110,
_2 = 8'b0101_1011, _3 = 8'b0100_1111,
_4 = 8'b0110_0110, _5 = 8'b0110_1101,
_6 = 8'b0111_1101, _7 = 8'b0000_0111,
_8 = 8'b0111_1111, _9 = 8'b0110_1111,
_0dot = 8'b1011_1111, _1dot = 8'b1000_0110,
_2dot = 8'b1101_1011, _3dot = 8'b1100_1111,
_4dot = 8'b1110_0110, _5dot = 8'b1110_1101,
_6dot = 8'b1111_1101, _7dot = 8'b1000_0111,
_8dot = 8'b1111_1111, _9dot = 8'b1110_1111,
_A = 8'b0111_0111, _B = 8'b0111_1100,
_C = 8'b0011_1001, _D = 8'b0101_1110,
_E = 8'b0111_1001, _F = 8'b0111_0001,
_M = 8'b1111_1111,_Dark = 8'b0000_0000;

always @ (*)
begin
case (BIT_CS_Current)
bit_0: Single_Seven_Segment_Code = iLed_SixCode[4:0];
bit_1: Single_Seven_Segment_Code = iLed_SixCode[9:5];
bit_2: Single_Seven_Segment_Code = iLed_SixCode[14:10];
bit_3: Single_Seven_Segment_Code = iLed_SixCode[19:15];
bit_4: Single_Seven_Segment_Code = iLed_SixCode[24:20];
bit_5: Single_Seven_Segment_Code = iLed_SixCode[29:25];
default : Single_Seven_Segment_Code = iLed_SixCode[4:0];
endcase
end



// translate hex code to 7 seg
reg [7:0] seven_segment_code;

always @ (*)
begin
case(Single_Seven_Segment_Code)
5'd0: seven_segment_code = _0;
5'd1: seven_segment_code = _1;
5'd2: seven_segment_code = _2;
5'd3: seven_segment_code = _3;
5'd4: seven_segment_code = _4;
5'd5: seven_segment_code = _5;
5'd6: seven_segment_code = _6;
5'd7: seven_segment_code = _7;
5'd8: seven_segment_code = _8;
5'd9: seven_segment_code = _9;
5'd10: seven_segment_code = _A;
5'd11: seven_segment_code = _B;
5'd12: seven_segment_code = _C;
5'd13: seven_segment_code = _D;
5'd14: seven_segment_code = _E;
5'd15: seven_segment_code = _F;
5'd16: seven_segment_code = _0dot;
5'd17: seven_segment_code = _1dot;
5'd18: seven_segment_code = _2dot;
5'd19: seven_segment_code = _3dot;
5'd20: seven_segment_code = _4dot;
5'd21: seven_segment_code = _5dot;
5'd22: seven_segment_code = _6dot;
5'd23: seven_segment_code = _7dot;
5'd24: seven_segment_code = _8dot;
5'd25: seven_segment_code = _9dot;
5'd31: seven_segment_code = _Dark;
default: seven_segment_code = _0;
endcase
end

assign Seven_Segment_code_Out = seven_segment_code;
assign Bit_Sel_Out = BIT_CS_Current;

reg [5:0] BIT_CS_next;

chunk_dff #(6) BIT_CS_DFF(.CLK(clk_600hz),
.D(BIT_CS_next),.Q(BIT_CS_Current));


//next state
always @ (*)
begin
case (BIT_CS_Current)
bit_0: BIT_CS_next = bit_1;
bit_1: BIT_CS_next = bit_2;
bit_2: BIT_CS_next = bit_3;
bit_3: BIT_CS_next = bit_4;
bit_4: BIT_CS_next = bit_5;
bit_5: BIT_CS_next = bit_0;
default:BIT_CS_next = bit_0;
endcase
end

endmodule

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