RFNoC完整开发流程记录

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1 前言

这篇文章以开发RFNoC-QPSK中的32bits-2bits转换模块为例演示RFNoC的完整开发流程, 并且起名"Outline", 希望通过这一篇文章能够快速回忆起流程. 因此这篇文章并不属于任何章节而是独立于书籍的根目录的存在.

注: 目前采用X310平台进行该流程

2 创建RFNoC Custom Module

这部分的详情见RFNoC工具链简介。

2.1 创建module

首先RFNoC module 是一个功能的工具集（类比gr-mod）。整个module包括多个blocks，共同组成某些功能的模块集合，我们首先就应该创建module。

➜ rfnocmodtool newmod --srcdir <UHD-Install-Prefix>/share/gr-ettus/rfnoc_modtool/rfnoc-newmod
Name of the new module: qpsk
Creating out-of-tree module in ./rfnoc-qpsk... Done.
Use 'rfnocmodtool add' to add a new block to this currently empty module.

其中<UHD-Install-Prefix>是UHD的安装路径。

2.2 添加block

创建module之后，我们向其中添加第一个功能模块——32bits-2bits转换。起名为conv32Bto2B，剩下的配置保持默认即可。

➜ cd rfnoc-qpsk
➜ rfnocmodtool add
RFNoC module name identified: qpsk
Enter name of block/code (without module name prefix): conv32Bto2B
Block/code identifier: conv32Bto2B
Enter valid argument list, including default arguments:
Add Python QA code? [y/N]
Add C++ QA code? [y/N]
Block NoC ID (Hexadecimal):
Random NoC ID generated: D6AA69D4
Skip Block Controllers Generation? [UHD block ctrl files] [y/N]
Skip Block interface files Generation? [GRC block ctrl files] [y/N]

3 功能实现

本节内容是要完成新创建RFNoC的功能部分，主要的流程就是FPGA编程+仿真确认功能的正确性，在RFNoC 4.0中提供了完整的仿真库，开发起来十分方便。

3.0 （更改NoC shell）

参考RFNoC CHDR 总线简介，我们知道CHDR包括context和payload两部分，如果是传统一进一出的数据处理模式，则不需要改变context的内容，但是在32位数据转2位数据的模式下，总线上的数据会变多。因此需要改变context的内容来告知CHDR数据变多（否则，CHDR只会读出与你输入数量相等的数据）。

而在CHDR数据转换为更加容易处理的axis的数据，RFNoC提供了两个（也许更多）的模块：chdr_to_axis_data和chdr_to_axis_pyld_ctxt。chdr_to_axis_pyld_ctxt直接将数据拆分为payload和context两部分，如果你想单独处理context的内容就需要进行手动的切片工作，对于不改变context内容的block，只需要将context的内容做透明转发即可。chdr_to_axis_data会继续把context上的内容继续拆分为timestamp, has_time, length, eov, eob以及payload部分data。

因为我们需要更改context的内容以告知总线数据被本模块倍增了，因此需要将默认的noc_shell生成的chdr_to_axis_pyld_ctxt更改为chdr_to_axis_data。

更改只需要参考rfnoc_block_duc的noc_shell_duc即可，只是用chdr_to_axis_data替换了chdr_to_axis_pyld_ctxt。

3.1 添加数据处理模块

为了保证程序的结构清晰，强烈建议不要在生成的文件中直接添加数据处理的代码，而是将数据处理单独封装成一个module，之后再在rfnoc_block_xxxx.v中实例化。

在本例中，我创建了QPSK_data_converter.v来实现数据的拆分转换。则要注意：在rfnocmodtool生成的文件之外创建的源文件，需要手动添加到编译目录中，打开rfnoc-<module name>/rfnoc/fpga/rfnoc_block_<block name>/Makefil.srcs，在RFNOC_OOT_SRCS中添加自定义文件！！

# Makefile.srcs

# RFNoC Block Sources
# Here, list all the files that are necessary to synthesize this block. Don't
# include testbenches!
# Make sure that the source files are nicely detectable by a regex. Best to put
# one on each line.
# The first argument to addprefix is the current path to this Makefile, so the
# path list is always absolute, regardless of from where we're including or
# calling this file. RFNOC_OOT_SRCS needs to be a simply expanded variable
# (not a recursively expanded variable), and we take care of that in the build
# infrastructure.
RFNOC_OOT_SRCS += $(addprefix $(dir $(abspath $(lastword $(MAKEFILE_LIST)))), rfnoc_block_conv32Bto2B.v noc_shell_conv32Bto2B.v QPSK_data_converter.v)

3.2 仿真模块功能

创建好数据处理模块之后，最好对其进行仿真分析，因为X310编译一次太久，提前完成数据分析有助于提前发现问题。

仿真的控制在rfnoc_block_<block name>_tb.sv文件中定义。启动仿真通过make rfnoc_block_<block name>_tb进行启动。

# cmake生成makefile
cmake -DUHD_FPGA_DIR=<uhd-repo>/fpga -DCMAKE_INSTALL_PREFIX=/opt/gr38uhd4105 ..
# 启动仿真
make rfnoc_block_conv32Bto2B_tb

如果想使用Qustasim进行更下细致的仿真，可以参考RFNoC block 仿真方法

3.3 创建FPGA镜像

makefile同样提供了编译FPGA镜像的快捷指令

make <block name>_x319_rfnoc_image_core

注意：这里有一个小bug，是yml文件定义的版本号为float，而处理脚本会将其当做string进行处理，因此需要手动将yml文件中的rfnoc_version的字段改为字符串，报错信息如下：

  File "/opt/gr38uhd4105/lib/python3.8/site-packages/uhd/imgbuilder/templates/rfnoc_image_core.vh.mako", line 3, in render_body
    protover = config.rfnoc_version.split('.')
AttributeError: 'ScalarFloat' object has no attribute 'split'

修改的文件包括

rfnoc/blocks/xxx.yml
rfnoc/icores/xxxx_x310_image_core.yml

4 安装RFNoC custom module

为了能正确的在gnuradio中调用自定义的module，需要运行编译安装。

cd <rfnoc module dir>/build
make install

5 在GNU Radio中测试模块功能

可以使用自动生成的grc进行测试

在这里对其稍微做出一点改动，框图如下。

在运行gr之前，需要将编译好的fpga镜像写入到x310中。

➜ uhd_image_loader --args="type=x300,addr=192.168.40.2" --fpga-path=<UHD-repo>/fpga/usrp3/top/x300/build-X310_HG/x300.bit
[INFO] [UHD] linux; GNU C++ version 9.3.0; Boost_107100; UHD_4.1.0.HEAD-0-g6bd0be9c
Unit: USRP X310 (31E24FC, 192.168.40.2)
FPGA Image: /home/lilacsat/Playground/rfnoc/src/uhd/fpga/usrp3/top/x300/build-X310_HG/x300.bit
-- Initializing FPGA loading...successful.
-- Loading FPGA image: 100% (121/121 sectors)
-- Finalizing image load...successful.
Power-cycle the USRP X310 to use the new image.

运行gr之前最好再用uhd_usrp_probe来确定镜像已经被正确加载。

➜ uhd_usrp_probe --args "addr=192.168.40.2"

[INFO] [UHD] linux; GNU C++ version 9.3.0; Boost_107100; UHD_4.1.0.HEAD-0-g6bd0be9c
[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Maximum frame size: 1472 bytes.
[WARNING] [X300] For the 192.168.40.2 connection, UHD recommends a send frame size of at least 8000 for best
performance, but your configuration will only allow 1472.This may negatively impact your maximum achievable sample rate.
Check the MTU on the interface and/or the send_frame_size argument.
[WARNING] [X300] For the 192.168.40.2 connection, UHD recommends a receive frame size of at least 8000 for best
performance, but your configuration will only allow 1472.This may negatively impact your maximum achievable sample rate.
Check the MTU on the interface and/or the recv_frame_size argument.
[INFO] [GPS] No GPSDO found
[INFO] [X300] Radio 1x clock: 200 MHz
[WARNING] [UDP] The recv buffer could not be resized sufficiently.
Target sock buff size: 24862979 bytes.
Actual sock buff size: 212992 bytes.
See the transport application notes on buffer resizing.
Please run: sudo sysctl -w net.core.rmem_max=24862979
[WARNING] [UDP] The send buffer could not be resized sufficiently.
Target sock buff size: 24862979 bytes.
Actual sock buff size: 212992 bytes.
See the transport application notes on buffer resizing.
Please run: sudo sysctl -w net.core.wmem_max=24862979
[WARNING] [UDP] The current recv_buff_size of 212992 is less than the minimum recommended size of 816000 and may result in dropped packets on some NICs
[WARNING] [UDP] The current send_buff_size of 212992 is less than the minimum recommended size of 307200 and may result in dropped packets on some NICs
[WARNING] [RFNOC::BLOCK_FACTORY] Could not find block with Noc-ID 0xd6aa69d4, 0xffff
  _____________________________________________________
 /
|       Device: X-Series Device
|     _____________________________________________________
|    /
|   |       Mboard: X310
|   |   revision: 11
|   |   revision_compat: 7
|   |   product: 30818
|   |   mac-addr0: 00:80:2f:30:ed:c5
|   |   mac-addr1: 00:80:2f:30:ed:c6
|   |   gateway: 192.168.10.1
|   |   ip-addr0: 192.168.10.2
|   |   subnet0: 255.255.255.0
|   |   ip-addr1: 192.168.20.2
|   |   subnet1: 255.255.255.0
|   |   ip-addr2: 192.168.30.2
|   |   subnet2: 255.255.255.0
|   |   ip-addr3: 192.168.40.2
|   |   subnet3: 255.255.255.0
|   |   serial: 31E24FC
|   |   FW Version: 6.0
|   |   FPGA Version: 38.0
|   |   FPGA git hash: 6bd0be9
|   |   
|   |   Time sources:  internal, external, gpsdo
|   |   Clock sources: internal, external, gpsdo
|   |   Sensors: ref_locked
|     _____________________________________________________
|    /
|   |       RFNoC blocks on this device:
|   |   
|   |   * 0/Block#0
|   |   * 0/DDC#0
|   |   * 0/DDC#1
|   |   * 0/DUC#0
|   |   * 0/DUC#1
|   |   * 0/Radio#0
|   |   * 0/Radio#1
|     _____________________________________________________
|    /
|   |       Static connections on this device:
|   |   
|   |   * 0/SEP#0:0==>0/DUC#0:0
|   |   * 0/DUC#0:0==>0/Radio#0:0
|   |   * 0/Radio#0:0==>0/DDC#0:0
|   |   * 0/DDC#0:0==>0/SEP#0:0
|   |   * 0/Radio#0:1==>0/DDC#0:1
|   |   * 0/DDC#0:1==>0/SEP#1:0
|   |   * 0/SEP#2:0==>0/DUC#1:0
|   |   * 0/DUC#1:0==>0/Radio#1:0
|   |   * 0/Radio#1:0==>0/DDC#1:0
|   |   * 0/DDC#1:0==>0/SEP#2:0
|   |   * 0/Radio#1:1==>0/DDC#1:1
|   |   * 0/DDC#1:1==>0/SEP#3:0
|   |   * 0/SEP#4:0==>0/Block#0:0
|   |   * 0/Block#0:0==>0/SEP#4:0
|     _____________________________________________________
|    /
|   |       TX Dboard: 0/Radio#0
|   |   ID: UBX-160 v2 (0x007d)
|   |   Serial: 31DE8D1
|   |     _____________________________________________________
|   |    /
|   |   |       TX Frontend: 0
|   |   |   Name: UBX TX
|   |   |   Antennas: TX/RX, CAL
|   |   |   Sensors: lo_locked
|   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
|   |   |   Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
|   |   |   Connection Type: QI
|   |   |   Uses LO offset: No
|     _____________________________________________________
|    /
|   |       RX Dboard: 0/Radio#0
|   |   ID: UBX-160 v2 (0x007e)
|   |   Serial: 31DE8D1
|   |     _____________________________________________________
|   |    /
|   |   |       RX Frontend: 0
|   |   |   Name: UBX RX
|   |   |   Antennas: TX/RX, RX2, CAL
|   |   |   Sensors: lo_locked
|   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
|   |   |   Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
|   |   |   Connection Type: IQ
|   |   |   Uses LO offset: No
|     _____________________________________________________
|    /
|   |       TX Dboard: 0/Radio#1
|   |   ID: Unknown (0x0094)
|   |   Serial: 3188C83
|   |     _____________________________________________________
|   |    /
|   |   |       TX Frontend: 0
|   |   |   Name: Unknown (0x0094) - 0
|   |   |   Antennas: 
|   |   |   Sensors: 
|   |   |   Freq range: 0.000 to 0.000 MHz
|   |   |   Gain Elements: None
|   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz
|   |   |   Connection Type: IQ
|   |   |   Uses LO offset: No
|     _____________________________________________________
|    /
|   |       RX Dboard: 0/Radio#1
|   |   ID: TwinRX Rev C (0x0095)
|   |   Serial: 3190DF9
|   |     _____________________________________________________
|   |    /
|   |   |       RX Frontend: 0
|   |   |   Name: TwinRX RX0
|   |   |   Antennas: RX1, RX2
|   |   |   Sensors: lo_locked
|   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   Gain range all: 0.0 to 93.0 step 1.0 dB
|   |   |   Bandwidth range: 80000000.0 to 80000000.0 step 0.0 Hz
|   |   |   Connection Type: II
|   |   |   Uses LO offset: No
|   |     _____________________________________________________
|   |    /
|   |   |       RX Frontend: 1
|   |   |   Name: TwinRX RX1
|   |   |   Antennas: RX1, RX2
|   |   |   Sensors: lo_locked
|   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   Gain range all: 0.0 to 93.0 step 1.0 dB
|   |   |   Bandwidth range: 80000000.0 to 80000000.0 step 0.0 Hz
|   |   |   Connection Type: QQ
|   |   |   Uses LO offset: No

测试结果

因为没有做幅值映射，只是将数据拆解开，放到最低两位，所以数据有4种情况。图中可见四种幅值的数据点。
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