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目录

本篇文章主要包含以下问题的解析，这部分是最基本的，不作解读。

1.Getting Started

1.1 Step one   赋值输出1

1.2 Zero  赋值输出0

2.Verilog Language 

——Problems that focus on introducing Verilog language syntax and features.

2.1 Basics    

1.Create a module with one input and one output that behaves like a wire.

2.Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:

 4.Create a module that implements a NOT gate.

5.Create a module that implements an AND gate.

6. Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

 7.Create a module that implements an XNOR gate.

 8.Declaring wires

 9.The 7458 is a chip with four AND gates and two OR gates. This problem is slightly more complex than 7420.

2.2 Vectors

1. Vectors

 2.Vectors in more detail

3. Vector part select

4.Bitwise operators

 5.Four-input gates

6.Vector concatenation operator

7.Vector reversal 1

8.Replication operator

9.More replication

1.Getting Started

1.1 Step one   赋值输出1

module top_module( output one );

// Insert your code here
    assign one = 1'b1;

endmodule

1.2 Zero  赋值输出0

module top_module(
    output zero
);// Module body starts after semicolon
    
assign zero=1'b0;
    
endmodule

2.Verilog Language 

——Problems that focus on introducing Verilog language syntax and features.

2.1 Basics    

1.Create a module with one input and one output that behaves like a wire.

module top_module( input in, output out );
assign out=in;
endmodule

2.Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:

module top_module( 
    input a,b,c,
    output w,x,y,z );
    
	assign w=a;
    assign x=b;
    assign y=b;
    assign z=c;
    
endmodule

 4.Create a module that implements a NOT gate.

module top_module( input in, output out );
	assign out=~in;
endmodule

5.Create a module that implements an AND gate.

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=a&b;

endmodule

6. Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

module top_module( 
    input a, 
    input b, 
    output out );
    
    assign out=~(a|b);
    
endmodule

 7.Create a module that implements an XNOR gate.

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=~(a^b);
endmodule

 8.Declaring wires

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
    
    wire e,f,g;
    
    assign e=a&b;
    assign f=c&d;
    assign g=e|f;
    assign out=g;
    assign out_n=~g;

endmodule

 9.The 7458 is a chip with four AND gates and two OR gates. This problem is slightly more complex than 7420.

Create a module with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs. You may choose to use an assign statement to drive each of the output wires, or you may choose to declare (four) wires for use as intermediate signals, where each internal wire is driven by the output of one of the AND gates. For extra practice, try it both ways.

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    assign p1y=(p1a&p1c&p1b)|(p1f&p1e&p1d);
    assign p2y=(p2a&p2b)|(p2c&p2d);


endmodule

2.2 Vectors

1. Vectors

Vectors are used to group related signals using one name to make it more convenient to manipulate.

For example, wire [7:0] w; declares

an 8-bit vector named w that is functionally equivalent to having 8 separate wires.

Notice that the declaration of a vector places the dimensions before the name of the vector, which is unusual compared to C syntax. However, the part select has the dimensions after the vector name as you would expect.

module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  ); // Module body starts after module declaration

 	assign outv=vec;
    assign o0=vec[0];
    assign o1=vec[1];
    assign o2=vec[2];
endmodule

 2.Vectors in more detail

`default_nettype none     // Disable implicit nets. Reduces some types of bugs.
module top_module( 
    input wire [15:0] in,
    output wire [7:0] out_hi,
    output wire [7:0] out_lo );
    
    assign out_hi=in[15:8];
    assign out_lo=in[7:0];
    
endmodule

3. Vector part select

A 32-bit vector can be viewed as containing 4 bytes (bits [31:24], [23:16], etc.). Build a circuit that will reverse the byte ordering of the 4-byte word.

AaaaaaaaBbbbbbbbCcccccccDddddddd => DdddddddCcccccccBbbbbbbbAaaaaaaa

This operation is often used when the endianness of a piece of data needs to be swapped, for example between little-endian x86 systems and the big-endian formats used in many Internet protocols.

module top_module( 
    input [31:0] in,
    output [31:0] out );//

    // assign out[31:24] = ...;
    assign out[31:24]=in[7:0];
    assign out[23:16]=in[15:8];
    assign out[15:8]=in[23:16];
    assign out[7:0]=in[31:24];
    
endmodule

4.Bitwise operators

Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not (i.e., bits [5:3]), and the inverse of a in the lower half.

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);
    assign out_or_bitwise=a|b;
    assign out_or_logical=a||b;
    assign out_not={~b,~a};

endmodule

 5.Four-input gates

Build a combinational circuit with four inputs, in[3:0].

There are 3 outputs:

• out_and: output of a 4-input AND gate.
• out_or: output of a 4-input OR gate.
• out_xor: output of a 4-input XOR gate.

• module top_module( 
      input [3:0] in,
      output out_and,
      output out_or,
      output out_xor
  );
  	assign out_and=∈
      assign out_or=|in;
      assign out_xor=^in;
  endmodule

  6.Vector concatenation operator

• Part selection was used to select portions of a vector. The concatenation operator {a,b,c} is used to create larger vectors by concatenating smaller portions of a vector together.

  {3'b111, 3'b000} => 6'b111000
  {1'b1, 1'b0, 3'b101} => 5'b10101
  {4'ha, 4'd10} => 8'b10101010     // 4'ha and 4'd10 are both 4'b1010 in binary

• 

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );//

    // assign { ... } = { ... };
    assign {w,x,y,z}={a,b,c,d,e,f,2'b11};
    
endmodule

7.Vector reversal 1

Given an 8-bit input vector [7:0], reverse its bit ordering.

module top_module( 
    input [7:0] in,
    output [7:0] out
);
    assign out={in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
endmodule

8.Replication operator

The concatenation operator allowed concatenating together vectors to form a larger vector. But sometimes you want the same thing concatenated together many times, and it is still tedious to do something like assign a = {b,b,b,b,b,b};. The replication operator allows repeating a vector and concatenating them together:

{num{vector}}

This replicates vector by num times. num must be a constant. Both sets of braces are required.

Examples:

{5{1'b1}}           // 5'b11111 (or 5'd31 or 5'h1f)
{2{a,b,c}}          // The same as {a,b,c,a,b,c}
{3'd5, {2{3'd6}}}   // 9'b101_110_110. It's a concatenation of 101 with
                    // the second vector, which is two copies of 3'b110.

A Bit of Practice

One common place to see a replication operator is when sign-extending a smaller number to a larger one, while preserving its signed value. This is done by replicating the sign bit (the most significant bit) of the smaller number to the left. For example, sign-extending 4'b0101 (5) to 8 bits results in 8'b00000101 (5), while sign-extending 4'b1101 (-3) to 8 bits results in 8'b11111101 (-3).

Build a circuit that sign-extends an 8-bit number to 32 bits. This requires a concatenation of 24 copies of the sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit number itself.

module top_module (
    input [7:0] in,
    output [31:0] out );//

    // assign out = { replicate-sign-bit , the-input };
    assign out={{24{in[7]}},in};
    
endmodule

9.More replication

Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise one-bit comparisons in the 25-bit output vector. The output should be 1 if the two bits being compared are equal.

out[24] = ~a ^ a;   // a == a, so out[24] is always 1.
out[23] = ~a ^ b;
out[22] = ~a ^ c;
...
out[ 1] = ~e ^ d;
out[ 0] = ~e ^ e;

module top_module (
    input a, b, c, d, e,
    output [24:0] out );//

    // The output is XNOR of two vectors created by 
    // concatenating and replicating the five inputs.
    // assign out = ~{ ... } ^ { ... };

    assign out=~{{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}}^{5{a,b,c,d,e}};


endmodule

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