Verilog HDLbits:Exams/2013 q2bfsm(有限元状态机)

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题目

Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input called resetn.

The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called state A. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).
FSM的工作方式如下。只要断言了复位输入，FSM就保持在开始状态，称为状态a。当复位信号被取消断言时，下一个时钟边缘之后，FSM必须将输出f设为1，持续一个时钟周期。然后，FSM必须监控x的输入。当x在三个连续的时钟周期中产生值1,0,1时，那么g应该在下一个时钟周期中设为1。当保持g = 1时，FSM必须监控y的输入。如果在两个时钟周期内y值至少有一次为1，则FSM需要永久保持g = 1(即直到复位)。但是如果在两个时钟周期内y没有变为1，则FSM应该将g永久设置为0(直到复位)。
(The original exam question asked for a state diagram only. But here, implement the FSM.)

分析

终于来到了状态机的最后一个题目，这个题看似复杂，实则只是多了几个状态而已，理清思路，画出状态转移图，这道题就迎刃而解了。
以下是我画出的状态转移图，供大家参考。由于题目要求输出f只拉高一个电平，所以使用start将F状态寄存起来。

代码如下

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
parameter idle=1,F=2,x1=3,x2=4,keep_g1=5,G=6,y1=7,start=8,keep_g0=9;
    reg [3:0] state,next_state;
    always@(*)
        case(state)
            idle:next_state=(resetn)?F:idle;
            F:next_state=start;
            start:next_state=(x)?x1:start;
            x1:next_state=(!x)?x2:x1;
            x2:next_state=(x)?G:start;
            G:next_state=(y)?keep_g1:y1;
            y1:next_state=(y)?keep_g1:keep_g0; 
            keep_g1:next_state=keep_g1;
            keep_g0:next_state=keep_g0;
         
        endcase
    always@(posedge clk)
        if(!resetn)
            state<=idle;
    else
        state<=next_state;
    assign f=(state==F);
    assign g=(state==keep_g1||state==y1||state==G);
            
    
endmodule

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